The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit improved in parasitic capacitance of a voltage-dividing resistance in a high voltage generating circuit for a memory device.
It has been required for development of a non-volatile semiconductor memory to realize a highly accurate control to a high output voltage level for a device withstand voltage, and write and erasing operations. FIG. 1 is a circuit diagram illustrative of a first conventional high voltage generating circuit for generating a highly accurate high voltage for writing and erasing operations of the non-volatile semiconductor memory. The first conventional high voltage generating circuit comprises a booster circuit 1, a comparator 2, and first and second voltage dividing resistances R1 and R2. The booster circuit 1 has a first input terminal for receiving a clock signal CLK and a second input terminal connected to an output terminal of the comparator 2 for receiving a control signal Vc from the comparator 2. The booster circuit 1 generates a high voltage output Vo which is outputted from its output terminal. A voltage dividing circuit is provided which comprises a series connection of the first and second voltage-dividing resistances R1 and R2 between the output terminal of the booster circuit 1 and a ground level. The first voltage-dividing resistance R1 is connected in series between the output terminal of the booster circuit 1 and the second voltage-dividing resistance R2. The second voltage-dividing resistance R2 is connected in series between the ground terminal and the first voltage-dividing resistance R1. The comparator 2 has a first input terminal connected to an output terminal of the voltage-dividing circuit or an intermediate point between the first and second voltage dividing resistances R1 and R2 for receiving a voltage Vi divided by the voltage-dividing circuit. The comparator 2 also has a second input terminal for receiving a reference voltage Vr for allowing the voltage Vi to be compared with the reference voltage Vr, whereby the comparator 2 generates the control signal Vc and output the same from its output terminal. The first voltage dividing resistance R1 has a first parasitic capacitance C2. The second voltage dividing resistance R2 has a second parasitic capacitance C3. Since the booster circuit 1 has a low capability of supplying the current, it is required to reduce the currents flowing through the series connections of the first and second voltage-dividing resistances R1 and R2, The resistance values of the first and second voltage-dividing resistances R1 and R2 are required to be high, provided that the high relative accuracy in resistance value of each of the first and second voltage-dividing resistances R1 and R2 is also necessary. For those purposes, the first and second voltage-dividing resistances R1 and R2 may further comprise polysilicon resistances which are low in bias-dependency and are suitable to be higher resistances than the diffusion resistances.
The first and second voltage-dividing resistances R1 and R2 need larger occupying areas than other resistances, whereby the larger occupying areas of the first and second voltage-dividing resistances R1 and R2 result in the increases in parasitic capacitances C2 and C3. The first voltage-dividing resistance R1 has a first time constant which is defined by the resistance value and the parasitic capacitance value thereof. The second voltage-dividing resistance R2 has a second time constant which is defined by the resistance value and the parasitic capacitance value thereof. The accuracy in the voltage level of the high voltage output depends on the time constant. As the time constants of the first and second voltage-dividing resistances R1 and R2 are increased, then the accuracy in the voltage level of the high voltage output is deteriorated. FIG. 2 is a diagram illustrative of the waveform of the high voltage output of the first conventional high voltage generating circuit of FIG. 1. FIG. 2 shows a ripple width xe2x80x9cvxe2x80x9d represented by a vertical arrow mark, an expected level represented by a horizontal broken line, delay times of the comparator represented by two horizontal short arrow marks and a delay of the voltage-dividing resistance represented by a horizontal long arrow mark. The first time constant defined by the first voltage-dividing resistance R1 and the first parasitic capacitance C2 and the second time constant defined by the second voltage-dividing resistance R2 and the second parasitic capacitance C3 cause a delay in time of the divided voltage Vi appearing on the output terminal between the first and second voltage-dividing resistances R1 and R2 of the voltage-dividing circuit. The delay in time of the divided voltage Vi increases a delay time of a feed-back path from the output terminal of the booster circuit 1 to the output terminal of the comparator 2. During this delay time period, it is difficult to control the booster circuit, whereby the high voltage output has a large ripple width and a deteriorated accuracy in its voltage level.
The ripple width is given by the following equation.
V={Dt1xc3x97(R1xc3x97C2)+Dt2}xc3x97Vdtxe2x80x83xe2x80x83(1)
where xe2x80x9cDt1xe2x80x9d is the delay of the voltage-dividing resistances, and xe2x80x9cDt2xe2x80x9d is the delay of the comparator, and xe2x80x9cVdtxe2x80x9d is a voltage rising rate per a unit time or a boosting capability. FIG. 3 is a diagram illustrative of a result of the simulation to the first conventional circuit of FIG. 1. The ripple width of the high voltage output is 700 mV. The large ripple width means the low accuracy in voltage level of the high voltage output. It is necessary for improving the accuracy in voltage level of the high voltage output to reduce the ripple width of the high voltage output- A second conventional high voltage generating circuit has been proposed for reducing the ripple width.
FIG. 4 is a circuit diagram illustrative of a second conventional high voltage generating circuit for generating a highly accurate high voltage for writing and erasing operations of the non-volatile semiconductor memory. The second conventional high voltage generating circuit further has a speed up capacitor C1. Namely, the second conventional high voltage generating circuit comprises a booster circuit 1, a comparator 2, and first and second voltage dividing resistances R1 and R2 as well as a capacitor C1 so called to as speed up capacitor. The booster circuit 1 has a first input terminal for receiving a clock signal CLK and a second input terminal connected to an output terminal of the comparator 2 for receiving a control signal Vc from the comparator 2. The booster circuit 1 generates a high voltage output Vo which is outputted from its output terminal. A voltage dividing circuit is provided which comprises a series connection of the first and second voltage-dividing resistances R1 and R2 between the output terminal of the booster circuit I and a ground level. The first voltage-dividing resistance R1 is connected in series between the output terminal of the booster circuit 1 and the second voltage-dividing resistance R2. The second voltage-dividing resistance R2 is connected in series between the ground terminal and the first voltage-dividing resistance R1. The comparator 2 has a first input terminal connected to an output terminal of the voltage-dividing circuit or an intermediate point between the first and second voltage dividing resistances R1 and R2 for receiving a voltage Vi divided by the voltage-dividing circuit, The comparator 2 also has a second input terminal for receiving a reference voltage Vr for allowing the voltage Vi to be compared with the reference voltage Vr, whereby the comparator 2 generates the control signal Vc and output the same from its output terminal. The first voltage dividing resistance R1 has a first parasitic capacitance C2. The second voltage dividing resistance R2 has a second parasitic capacitance C3. The capacitor C1 as the speed up capacitor is connected between the output terminal of the booster circuit 1 and the first input terminal of the comparator 2. Namely, the capacitor C1 as the speed tip capacitor is connected between the output terminal of the booster circuit 1 and the output terminal of the voltage-dividing circuit. The further provision of the speed up capacitor C1 for reducing the ripple width causes the increase in the occupied area of the second conventional high voltage generating circuit. FIG. 5 is a diagram illustrative of a result of the simulation to the second conventional circuit of FIG. 4. The ripple width of the high voltage output is reduced to 300 mV, provided that the speed up capacitance C1 is 0.3 pF. The further provision of the speed up capacitor of the second conventional high voltage generating circuit reduces the ripple width or improves the accuracy in voltage level of the high voltage output, however, with the increase in the occupied area of the high voltage generating circuit.
In the above circumstances, it had been required to develop a novel high voltage generating circuit free from the above problem.
Accordingly, it is an object of the present invention to provide a novel high voltage generating circuit free from the above problems.
It is a further object of the present invention to provide a novel high voltage generating circuit with a suppressed increase in occupied area of the circuit even a speed up capacitor is further provided.
It is a still further object of the present invention to provide a novel high voltage generating circuit reduced in ripple width.
It is yet a further object of the present invention to provide a novel high voltage generating circuit improved in accuracy in voltage level of a high voltage output.
The present invention provides a circuitry comprising; a first circuit for rising a voltage level, the first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output; a comparator having an output terminal connected to an input side of the first circuit, the comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and a voltage dividing circuit connected between the high voltage output line and a low voltage line having a substantially fixed lower potential than the high voltage output line, the voltage dividing circuit having an output node which is connected to the first input terminal of the comparator for outputting a divided voltage output; and the voltage dividing circuit having at least a resistance between the output node and the high voltage output line, wherein a parasitic capacitance of the at least resistance between the output node and the high voltage output line is connected to the high voltage output line.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.